diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/irqs.h linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/irqs.h --- linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/irqs.h 2007-02-04 18:44:54.000000000 +0000 +++ linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/irqs.h 2007-02-12 14:32:19.000000000 +0000 @@ -34,10 +34,10 @@ #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ #define IRQ_EINT8t23 S3C2410_IRQ(5) #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ -#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */ +#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ #define IRQ_BATT_FLT S3C2410_IRQ(7) #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ -#define IRQ_WDT S3C2410_IRQ(9) +#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ #define IRQ_TIMER0 S3C2410_IRQ(10) #define IRQ_TIMER1 S3C2410_IRQ(11) #define IRQ_TIMER2 S3C2410_IRQ(12) @@ -45,7 +45,7 @@ #define IRQ_TIMER4 S3C2410_IRQ(14) #define IRQ_UART2 S3C2410_IRQ(15) #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ -#define IRQ_DMA0 S3C2410_IRQ(17) +#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ #define IRQ_DMA1 S3C2410_IRQ(18) #define IRQ_DMA2 S3C2410_IRQ(19) #define IRQ_DMA3 S3C2410_IRQ(20) @@ -94,6 +94,8 @@ * these need to be ordered in number of appearance in the * SUBSRC mask register */ +#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) + #define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */ #define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */ #define IRQ_S3CUART_ERR0 S3C2410_IRQ(56) @@ -111,12 +113,39 @@ /* extra irqs for s3c2440 */ -#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65) -#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66) +#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65) /* S3C2443 */ +#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66) /* S3C2443 */ #define IRQ_S3C2440_WDT S3C2410_IRQ(67) #define IRQ_S3C2440_AC97 S3C2410_IRQ(68) -#define NR_IRQS (IRQ_S3C2440_AC97+1) +/* irqs for s3c2443 */ + +#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ +#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ +#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ +#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */ +#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ + +#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) +#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) +#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) +#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) + +#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) +#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) +#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) +#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) +#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) +#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) + +#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) +#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) +#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) + +#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) +#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) + +#define NR_IRQS (IRQ_S3C2443_AC97+1) #endif /* __ASM_ARCH_IRQ_H */ diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-clock.h linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-clock.h --- linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-clock.h 2007-02-04 18:44:54.000000000 +0000 +++ linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-clock.h 2007-02-15 11:38:52.000000000 +0000 @@ -100,6 +100,7 @@ s3c2410_get_pll(unsigned int pllval, uns return (unsigned int)fvco; } + #endif /* __ASSEMBLY__ */ #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) @@ -190,4 +191,5 @@ s3c2410_get_pll(unsigned int pllval, uns #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ + #endif /* __ASM_ARM_REGS_CLOCK */ diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-gpio.h linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-gpio.h --- linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-gpio.h 2007-02-04 18:44:54.000000000 +0000 +++ linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-gpio.h 2007-02-12 14:04:17.000000000 +0000 @@ -201,7 +201,7 @@ #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) -/* no i/o pin in port b can have value 3! */ +/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) #define S3C2410_GPB0_INP (0x00 << 0) @@ -242,6 +242,7 @@ #define S3C2410_GPB5_INP (0x00 << 10) #define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10) +#define S3C2443_GPB5_XBACK (0x03 << 10) #define S3C2400_GPB5_DATA21 (0x02 << 10) #define S3C2400_GPB5_nCTS1 (0x03 << 10) @@ -249,6 +250,7 @@ #define S3C2410_GPB6_INP (0x00 << 12) #define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12) +#define S3C2443_GPB6_XBREQ (0x03 << 12) #define S3C2400_GPB6_DATA22 (0x02 << 12) #define S3C2400_GPB6_nRTS1 (0x03 << 12) @@ -256,6 +258,7 @@ #define S3C2410_GPB7_INP (0x00 << 14) #define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14) +#define S3C2443_GPB7_XDACK1 (0x03 << 14) #define S3C2400_GPB7_DATA23 (0x02 << 14) #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) @@ -268,6 +271,7 @@ #define S3C2410_GPB9_INP (0x00 << 18) #define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18) +#define S3C2443_GPB9_XDACK0 (0x03 << 18) #define S3C2400_GPB9_DATA25 (0x02 << 18) #define S3C2400_GPB9_I2SSDI (0x03 << 18) @@ -275,6 +279,7 @@ #define S3C2410_GPB10_INP (0x00 << 20) #define S3C2410_GPB10_OUTP (0x01 << 20) #define S3C2410_GPB10_nXDRE0 (0x02 << 20) +#define S3C2443_GPB10_XDREQ0 (0x03 << 20) #define S3C2400_GPB10_DATA26 (0x02 << 20) #define S3C2400_GPB10_nSS (0x03 << 20) @@ -556,6 +561,7 @@ #define S3C2410_GPE0_INP (0x00 << 0) #define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0) +#define S3C2443_GPE0_AC_nRESET (0x03 << 0) #define S3C2400_GPE0_EINT0 (0x02 << 0) #define S3C2410_GPE0_MASK (0x03 << 0) @@ -563,6 +569,7 @@ #define S3C2410_GPE1_INP (0x00 << 2) #define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2) +#define S3C2443_GPE1_AC_SYNC (0x03 << 2) #define S3C2400_GPE1_EINT1 (0x02 << 2) #define S3C2400_GPE1_nSS (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2) @@ -571,6 +578,7 @@ #define S3C2410_GPE2_INP (0x00 << 4) #define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4) +#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) #define S3C2400_GPE2_EINT2 (0x02 << 4) #define S3C2400_GPE2_I2SSDI (0x03 << 4) @@ -578,6 +586,7 @@ #define S3C2410_GPE3_INP (0x00 << 6) #define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6) +#define S3C2443_GPE3_AC_SDI (0x03 << 6) #define S3C2400_GPE3_EINT3 (0x02 << 6) #define S3C2400_GPE3_nCTS1 (0x03 << 6) #define S3C2410_GPE3_nSS0 (0x03 << 6) @@ -587,6 +596,7 @@ #define S3C2410_GPE4_INP (0x00 << 8) #define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8) +#define S3C2443_GPE4_AC_SDO (0x03 << 8) #define S3C2400_GPE4_EINT4 (0x02 << 8) #define S3C2400_GPE4_nRTS1 (0x03 << 8) #define S3C2410_GPE4_I2SSDI (0x03 << 8) @@ -596,6 +606,7 @@ #define S3C2410_GPE5_INP (0x00 << 10) #define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10) +#define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) @@ -603,24 +614,32 @@ #define S3C2410_GPE6_INP (0x00 << 12) #define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_SDCMD (0x02 << 12) +#define S3C2443_GPE6_SD1_CMD (0x02 << 12) +#define S3C2443_GPE6_AC_BITCLK (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) #define S3C2410_GPE7_INP (0x00 << 14) #define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) +#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) +#define S3C2443_GPE7_AC_SDI (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) #define S3C2410_GPE8_INP (0x00 << 16) #define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) +#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) +#define S3C2443_GPE8_AC_SDO (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) #define S3C2410_GPE9_INP (0x00 << 18) #define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) +#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) +#define S3C2443_GPE9_AC_SYNC (0x03 << 18) #define S3C2400_GPE9_nXDACK1 (0x02 << 18) #define S3C2400_GPE9_nXBACK (0x03 << 18) @@ -628,6 +647,8 @@ #define S3C2410_GPE10_INP (0x00 << 20) #define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) +#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) +#define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) @@ -796,6 +817,7 @@ #define S3C2400_GPG4_MMCCLK (0x02 << 8) #define S3C2400_GPG4_I2SSDI (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8) +#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) #define S3C2410_GPG5_INP (0x00 << 10) @@ -803,7 +825,7 @@ #define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2400_GPG5_MMCCMD (0x02 << 10) #define S3C2400_GPG5_IICSDA (0x03 << 10) -#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) +#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) #define S3C2410_GPG6_INP (0x00 << 12) @@ -845,6 +867,7 @@ #define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22) +#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) #define S3C2410_GPG12_INP (0x00 << 24) @@ -852,25 +875,28 @@ #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2442_GPG12_nSPICS0 (0x03 << 24) +#define S3C2443_GPG12_nINPACK (0x03 << 24) #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) #define S3C2410_GPG13_INP (0x00 << 26) #define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_EINT21 (0x02 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26) +#define S3C2443_GPG13_CF_nREG (0x03 << 26) #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) #define S3C2410_GPG14_INP (0x00 << 28) #define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_EINT22 (0x02 << 28) #define S3C2410_GPG14_YMON (0x03 << 28) +#define S3C2443_GPG14_CF_RESET (0x03 << 28) #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) #define S3C2410_GPG15_INP (0x00 << 30) #define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_EINT23 (0x02 << 30) #define S3C2410_GPG15_nYPON (0x03 << 30) - +#define S3C2443_GPG15_CF_PWR (0x03 << 30) #define S3C2410_GPG_PUPDIS(x) (1<<(x)) diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h --- linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h 2007-02-15 11:40:29.000000000 +0000 @@ -0,0 +1,192 @@ +/* linux/include/asm-arm/arch-s3c2410/regs-clock.h + * + * Copyright (c) 2007 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2443 clock register definitions +*/ + +#ifndef __ASM_ARM_REGS_S3C2443_CLOCK +#define __ASM_ARM_REGS_S3C2443_CLOCK + +#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) + +#define S3C2443_PLLCON_MDIVSHIFT 16 +#define S3C2443_PLLCON_PDIVSHIFT 8 +#define S3C2443_PLLCON_SDIVSHIFT 0 +#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) +#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) +#define S3C2443_PLLCON_SDIVMASK (3) + +#define S3C2443_MPLLCON S3C2443_CLKREG(0x10) +#define S3C2443_EPLLCON S3C2443_CLKREG(0x18) +#define S3C2443_CLKSRC S3C2443_CLKREG(0x20) +#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) +#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) +#define S3C2443_HCLKCON S3C2443_CLKREG(0x30) +#define S3C2443_PCLKCON S3C2443_CLKREG(0x34) +#define S3C2443_SCLKCON S3C2443_CLKREG(0x38) +#define S3C2443_PWRMODE S3C2443_CLKREG(0x40) +#define S3C2443_SWRST S3C2443_CLKREG(0x44) +#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) +#define S3C2443_SYSID S3C2443_CLKREG(0x5C) +#define S3C2443_PWRCFG S3C2443_CLKREG(0x60) +#define S3C2443_RSTCON S3C2443_CLKREG(0x64) + +#define S3C2443_PLLCON_OFF (1<<24) + +#define S3C2443_CLKSRC_I2S_EXT (1<<14) +#define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14) +#define S3C2443_CLKSRC_I2S_EPLLREF (2<<14) +#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) +#define S3C2443_CLKSRC_I2S_MASK (3<<14) + +#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8) +#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8) +#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8) +#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8) +#define S3C2443_CLKSRC_EPLLREF_MASK (3<<8) + +#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) +#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) +#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) + +#define S3C2443_CLKDIV0_DVS (1<<13) +#define S3C2443_CLKDIV0_HALF_HCLK (1<<3) +#define S3C2443_CLKDIV0_HALF_PCLK (1<<2) + +#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) + +#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) +#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) + +#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) +#define S3C2443_CLKDIV0_PREDIV_SHIFT (4) + +#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) +#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) +#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) +#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) +#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) +#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) +#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) +#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) +#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) +#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) + +/* S3C2443_CLKDIV1 */ + +#define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26) +#define S3C2443_CLKDIV1_CAMDIV_SHIFT (26) + +#define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24) +#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24) + +#define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16) +#define S3C2443_CLKDIV1_DISPDIV_SHIFT (16) + +#define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12) +#define S3C2443_CLKDIV1_I2SDIV_SHIFT (12) + +#define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8) +#define S3C2443_CLKDIV1_UARTDIV_SHIFT (8) + +#define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6) +#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6) + +#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4) +#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4) + +#define S3C2443_CLKCON_NAND + +#define S3C2443_HCLKCON_DMA0 (1<<0) +#define S3C2443_HCLKCON_DMA1 (1<<1) +#define S3C2443_HCLKCON_DMA2 (1<<2) +#define S3C2443_HCLKCON_DMA3 (1<<3) +#define S3C2443_HCLKCON_DMA4 (1<<4) +#define S3C2443_HCLKCON_DMA5 (1<<5) +#define S3C2443_HCLKCON_CAMIF (1<<8) +#define S3C2443_HCLKCON_DISP (1<<9) +#define S3C2443_HCLKCON_LCDC (1<<10) +#define S3C2443_HCLKCON_USBH (1<<11) +#define S3C2443_HCLKCON_USBD (1<<12) +#define S3C2443_HCLKCON_HSMMC (1<<16) +#define S3C2443_HCLKCON_CFC (1<<17) +#define S3C2443_HCLKCON_SSMC (1<<18) +#define S3C2443_HCLKCON_DRAMC (1<<19) + +#define S3C2443_PCLKCON_UART0 (1<<0) +#define S3C2443_PCLKCON_UART1 (1<<1) +#define S3C2443_PCLKCON_UART2 (1<<2) +#define S3C2443_PCLKCON_UART3 (1<<3) +#define S3C2443_PCLKCON_IIC (1<<4) +#define S3C2443_PCLKCON_SDI (1<<5) +#define S3C2443_PCLKCON_ADC (1<<7) +#define S3C2443_PCLKCON_IIS (1<<9) +#define S3C2443_PCLKCON_PWMT (1<<10) +#define S3C2443_PCLKCON_WDT (1<<11) +#define S3C2443_PCLKCON_RTC (1<<12) +#define S3C2443_PCLKCON_GPIO (1<<13) +#define S3C2443_PCLKCON_SPI0 (1<<14) +#define S3C2443_PCLKCON_SPI1 (1<<15) + +#define S3C2443_SCLKCON_DDRCLK (1<<16) +#define S3C2443_SCLKCON_SSMCCLK (1<<15) +#define S3C2443_SCLKCON_HSSPICLK (1<<14) +#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) +#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) +#define S3C2443_SCLKCON_CAMCLK (1<<11) +#define S3C2443_SCLKCON_DISPCLK (1<<10) +#define S3C2443_SCLKCON_I2SCLK (1<<9) +#define S3C2443_SCLKCON_UARTCLK (1<<8) +#define S3C2443_SCLKCON_USBHOST (1<<1) + +#include + +static inline unsigned int +s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; + pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; + sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; + + mdiv &= S3C2443_PLLCON_MDIVMASK; + pdiv &= S3C2443_PLLCON_PDIVMASK; + sdiv &= S3C2443_PLLCON_SDIVMASK; + + fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); + do_div(fvco, pdiv << sdiv); + + return (unsigned int)fvco; +} + +static inline unsigned int +s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; + pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; + sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; + + mdiv &= S3C2443_PLLCON_MDIVMASK; + pdiv &= S3C2443_PLLCON_PDIVMASK; + sdiv &= S3C2443_PLLCON_SDIVMASK; + + fvco = (uint64_t)baseclk * (mdiv + 8); + do_div(fvco, (pdiv + 2) << sdiv); + + return (unsigned int)fvco; +} + +#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ + diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-serial.h linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-serial.h --- linux-2.6.20-rmk-12feb2007/include/asm-arm/arch-s3c2410/regs-serial.h 2007-02-04 18:44:54.000000000 +0000 +++ linux-2.6.20-rmk-12feb2007-s3c2443-1-sub/include/asm-arm/arch-s3c2410/regs-serial.h 2007-02-14 01:30:40.000000000 +0000 @@ -35,10 +35,12 @@ #define S3C24XX_VA_UART0 (S3C24XX_VA_UART) #define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) #define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) +#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 ) #define S3C2410_PA_UART0 (S3C24XX_PA_UART) #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) +#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) #define S3C2410_URXH (0x24) #define S3C2410_UTXH (0x20) @@ -73,6 +75,8 @@ #define S3C2440_UCON_UCLK (1<<10) #define S3C2440_UCON_PCLK2 (2<<10) #define S3C2440_UCON_FCLK (3<<10) +#define S3C2443_UCON_EPLL (3<<10) + #define S3C2440_UCON2_FCLK_EN (1<<15) #define S3C2440_UCON0_DIVMASK (15 << 12) #define S3C2440_UCON1_DIVMASK (15 << 12) @@ -93,6 +97,8 @@ #define S3C2410_UCON_TXIRQMODE (1<<2) #define S3C2410_UCON_RXIRQMODE (1<<0) #define S3C2410_UCON_RXFIFO_TOI (1<<7) +#define S3C2443_UCON_RXERR_IRQEN (1<<6) +#define S3C2443_UCON_LOOPBACK (1<<5) #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -127,7 +133,7 @@ #define S3C2410_UMCOM_AFC (1<<4) #define S3C2410_UMCOM_RTS_LOW (1<<0) -#define S3C2412_UMCON_AFC_63 (0<<5) +#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */ #define S3C2412_UMCON_AFC_56 (1<<5) #define S3C2412_UMCON_AFC_48 (2<<5) #define S3C2412_UMCON_AFC_40 (3<<5) @@ -143,6 +149,7 @@ #define S3C2410_UFSTAT_RXMASK (15<<0) #define S3C2410_UFSTAT_RXSHIFT (0) +/* UFSTAT S3C2443 same as S3C2440 */ #define S3C2440_UFSTAT_TXFULL (1<<14) #define S3C2440_UFSTAT_RXFULL (1<<6) #define S3C2440_UFSTAT_TXSHIFT (8) @@ -157,6 +164,8 @@ #define S3C2410_UERSTAT_OVERRUN (1<<0) #define S3C2410_UERSTAT_FRAME (1<<2) #define S3C2410_UERSTAT_BREAK (1<<3) +#define S3C2443_UERSTAT_PARITY (1<<1) + #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ S3C2410_UERSTAT_FRAME | \ S3C2410_UERSTAT_BREAK) @@ -164,6 +173,8 @@ #define S3C2410_UMSTAT_CTS (1<<0) #define S3C2410_UMSTAT_DeltaCTS (1<<2) +#define S3C2443_DIVSLOT (0x2C) + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc